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Call For Paper is Open for Vol.7 No.2 September 2022, Please submit paper Vol. 4 No. 1 - (March 2019)

DOI

Paper Title

10.21058/gjecs.2019.41001

Frequency Scaled Green Data Flip Flop on Different Nanometer Technology Based FPGA

Author Name

Volume No., Issue No., Year, & Page No.

Keshav Kumar, Srishti Priya Chaturvedi, Bishwajeet Pandey, Rajina R. Mohamed

Vol. 4, No. 1, March 2019, pp. 1-7

Abstract:

In order to meet the energy requirement of the total population of the globe, we have designed an energy efficient data flip flop on different nanometer technology based FPGA. We used frequency scaling technique in order to analyze power dissipation. The power has been analyzes for Virtex 6 (40nm) FPGA, Spartan 3 (90nm) FPGA, Spartan 6 (45nm FPGA). We varied the frequency from 10 MHz to 100 GHz and observed the different powers of chips which are clustered on data flip flop, e.g. Clocks, Signals, I/O, Leakage, and Total power. We observed that at low frequency, there is less power dissipation whereas at high frequency more power is dissipated.

Keywords:

Spartan 6, Spartan 3, Virtex 6, FPGA, Power, Frequency

Full Text:

References:

  1. Energy Crisis, Last Accessed on 3rd January 2019, en.wikipedia.org/wiki/Energy_crisis.
  2. D. Jones, and D. M. Lewis. "A time-multiplexed FPGA architecture for logic emulation." In Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, pp. 495-498. IEEE, 1995.
  3. S. Trimberger, D. Carberry, A. Johnson, and J. Wong. "A time-multiplexed FPGA." In Field-Programmable Custom Computing Machines, 1997. Proceedings., the 5th Annual IEEE Symposium on, pp. 22-28. IEEE, 1997.
  4. L. Shang, A. S. Kaviani, and K. Bathala. "Dynamic power consumption in Virtex™-II FPGA family." In Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, pp. 157-164. ACM, 2002.
  5. W. Zhao, E. Belhaire, V. Javerliac, C. Chappert, and B. Dieny. "A non-volatile flip-flop in magnetic FPGA chip." In Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on, pp. 323-326. IEEE, 2006.
  6. S. Singh, A. Kaur and B. Pandey, 2014, December. Energy efficient flip flop design using voltage scaling on FPGA. In Power Electronics (IICPE), 2014 IEEE 6th India International Conference on (pp. 1-5). IEEE.
  7. F. Serrano, J. A. Clemente, and H. Mecha. "A methodology to emulate single event upsets in flip-flops using FPGAs through partial reconfiguration and instrumentation." IEEE Transactions on Nuclear Science 62, no. 4 (2015): 1617-1624

DOI

Paper Title

10.21058/gjecs.2019.41002

Energy Efficient UART Design Using Virtex-4, Virtex-5 and Virtex-6 FPGA

Author Name

Volume No., Issue No., Year, & Page No.

Keshav Kumar, Amanpreet Kaur

Vol. 4, No. 1, March 2019, 8-13

Abstract

We analyzed the deviation of various power of chips that are clustered on Universal Asynchronous Receiver Transmitter (UART), for example IOs power, leakage power and total power by varying the voltage supply. We performed our experiment and analyzed how the variation in voltage influences the power of UART chips. We used three different FPGA technology that are Virtex-4, Virtex-5, and Virtex-6 to perform our experiment and analyzed that Virtex-4 is most power efficient.

Keywords:

Virtex-4, Virtex-5, Virtex-6, FPGA, Power, Voltage, UART.

Full Text:

References:

  1. Energy Crisis, en.wikipedia.org/wiki/Energy_crisis, Last Accessed on 28th January 2019
  2. D. Bhadra, V. S. Vij, and K. S. Stevens. "A low power UART design based on asynchronous techniques." In Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on, pp. 21-24. IEEE, 2013.
  3. A. Kaur, B. Pandey, A. Sharma, K. Sharma, and S. Singh. "SSTL IO Standard Based Tera Hertz and Energy Efficient MALAYALAM Unicode Reader Design and Implementation on FPGA." In DRDO, Ministry of Defence, Government of India: Bilingual International Conference on Information Technology at Defence Scientific Information and Documentation Centre (DESIDOC), pp. 19-21. 2015..
  4. S.Yu, L. Yi, W. Chen, and Z. Wen, “Implementation of a multichannel uart controller based on fifo technique and fpga”, in Industrial Electronics and Application.2007. ICIEA 2007. 2nd IEEE Confrence on, may 2007,pp.2633-2638.
  5. M. Idris and M. Yaacob, “A vhdl implementation of bist technique in uart design,” in TENCON 2003. Conference on Convergent Technologie for the Asia-Pacific Region, vol. 4, Oct., pp. 1450–1454 Vol.4.
  6. J. Norhuzaimin and H. H. Maimun, “The design of high speed uart,” in Applied Electromagnetics, 2005. APACE 2005. Asia-Pacific Conference on, Dec., pp. 5 pp.
  7. Ed. Peterson, "Developing tamper resistant designs with Xilinx Virtex-6 and 7 series FPGAs." Application Note. Xilinx Corporation (2013).
  8. J. H. Anderson, and F. N. Najm. "Active leakage power optimization for FPGAs." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems25, no. 3 (2006): 423-437.
  9. A. Peggy, M. Klein, and B. Philofsky. "Virtex-5 FPGA system power design considerations." Xilinx WP285 (v1. 0) February 14 (2008).

DOI

Paper Title

10.21058/gjecs.2019.41003

Towards the implementation of Internet of Things

Author Name

Volume No., Issue No., Year, & Page No.

Pardeep Kumar, Saleemullah Jamali

Vol. 4, No. 1, March 2019, 14-24

Abstract

The Internet of Things (IoT) is a fast-expanding innovation that aims making several things / objects communicate with each other in a large heterogeneous environment. Lately, several ideas and schemes have been proposed by researchers in order to move further towards the realization of such a complex and challenging network. This paper discourses the overall requirements, challenges, merits, demerits and comparison of different operating systems, simulators, testbeds and architectures that have been proposed specifically for IoT. Additionally, a novel IoT architecture that intends to deal with standardization, interoperability, integration, security, etc., related issues of IoT has also been proposed in this paper.

Keywords:

IoT, simulation, operating systems, testbed, architecture, security, intelligence, management layer

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References:

  1. D. Miorandi, S. Sicari, F. D. Pellegrini, and I. Chlamtac, “Internet of things: Vision, applications and research challenges,” International Journal of Ad Hoc Networks, vol. 10, pp. 1497–1516, 2012.
  2. J. Lin, W. Yu, N. Zhang, X. Yang, H. Zhang and W. Zhao, "A Survey on Internet of Things: Architecture, Enabling Technologies, Security and Privacy, and Applications," in IEEE Internet of Things Journal, vol. 4, no. 5, pp. 1125-1142, Oct. 2017.
  3. R. Petrolo, N. Mitton, J. Soldatos, M. Hauswirth, and G. Schiele, “Inte- grating Wireless Sensor Networks within a City Cloud,” in International IEEE SECON Workshop on Self-Organizing Wireless Access Networks for Smart City, Singapore, June 2014.
  4. M. Jevtic and N. Zogovic, “Evaluation of Wireless Sensor Network Sim- ulators,” in 17th Telecommunications forum TELFOR, Serbia, Belgrade, November 24-26 2009.
  5. Zeinab K A Mohammed and Elmustafa S A Ahmed, “Internet of Things Applications, Challenges and related future technologies”, World Scientific News, Vol. 67, no. 2, pp. 126-148,2017.
  6. T. Reusing, “Comparison of Operating Systems TinyOS and Contiki,” in Seminar: Sensor Nodes Operation, Network and Application (SN), Summer Semester 2012, Munich, Germany, August 2012, pp. 7–14, volume NET-2012-08-2 of Network Architectures and Services (NET).
  7. T. Borgohain, U. Kumar, and S. Sanyal, “Survey of operating systems for the iot environment,” International Journal of Advanced Networking and Applications, vol. 6, no. 5, pp. 2479–2483, 2015.
  8. E. Baccelli, O. Hahm, M. Wahlisch, M. Guenes, and T. Schmidt, “RIOT: One OS to Rule Them All in the IoT,” [Research Report] RR-8176, 2012.
  9. T. Paul and G. S. Kumar, “Safe Contiki OS: Type and Memory Safety for Contiki OS,” in International Conference on Advances in Recent Technologies in Communication and Computing, October 2009, pp. 169–171.
  10. S. Rampfl, “Network Simulation and its Limitations,” in Seminars FI / IITM / ACN SS2013, Network Architectures and Services, August 2013, pp. 57–63.
  11. B. Sobhan babu, P. Lakshmi Padmaja, T. Ramanjaneyulu et.al, “Role of COOJA Simulator in IoT”, International Journal of Emerging Trends & Technology in Computer Science (IJETTCS), Vol. 6, no. 2, March – April, pp. 139-143, 2017.
  12. C. Tapparello, H. Ayatollahi, and W. Heinzelman, “Energy Harvesting Framework for Network Simulator 3 (ns-3),” in 2nd International Workshop on Energy Neutral Sensing Systems (ENSsys14), Memphis, TN, USA, November 06 2014, pp. 37–42.
  13. D. Pediaditakis, Y. Tselishchev, and A. Boulis, “Performance and Scala- bility Evaluation of the Castalia Wireless Sensor Network Simulator,” in 3rd International ICST Conference on Simulation Tools and Techniques (SIMUTools10), Brussels, Belgium, 2010.
  14. A.-S. Tonneau, N. Mitton, and J. Vandaele, “A Survey on (mobile) wireless sensor network experimentation testbeds,” in DCOSS - IEEE International Conference on Distributed Computing in Sensor Systems, Marina Del Rey, California, United States, May 2014.
  15. L. Sanchez, L. Munoz, and J. A. Galachel, “SmartSantander: IoT experimentation over a smart city testbed,” International Journal of Computer Networks, vol. 61, pp. 217–238, March 2014.
  16. M. Guenes, O. Hahm, and K. Schleiser, “DES-Testbed A Wireless Multi- Hop Network Testbed for future mobile networks,” 2010.
  17. O. Fambon, E. Fleury, G. Harter, R. Pissard-Gibollet, and F. Saint- Marcel, “FIT IoT-LAB tutorial: hands-on practice with a very large scale testbed tool for the Internet of Things,” in 10mes journes francophones Mobilit et Ubiquit (UbiMob), Sophia-Antipolis, 5-6 June 2014.
  18. L. Tan and N. Wang, “Future Internet: The Internet of Things,” in 3rd In- ternational Conference on Advanced Computer Theory and Engineering (ICACTE), Chengdu, China, August 2010, pp. 376–380.
  19. T. Fan and Y. Chen, “A scheme of data management in the Internet of Things,” in 2nd International Conference on Network Infrastructure and Digital Content, Beijing, China, September 2010, pp. 110–114.
  20. S. Jamali, P. Kumar, and U. Ali, “Internet of Things: Architecture and Integration with Other Networks,” in 1st International Conference on Modern Communication and Computing Technologies, MCCT14, Nawabshah, Pakistan, 26-28 February 2014.
  21. Antonio Linan Colina, A Vives, M Zennaro, A Bagula, E Pietrosemoli, “Internet of Things in five days”, IPv6 WSN Book v1.1, pp. 1-227, June 2016.

Vol. 4 No. 2 - (September 2019)

DOI

Paper Title

10.21058/gjecs.2019.42001

Vortex Furnace or Vortex Mixer in Life Furnaces

Author Name

Volume No., Issue No., Year, & Page No.

Svetlana Zakharchenko, Nikolay Zakharchenko, Sabina Nedbailik, Ernest Tsypkin

Vol. 4, No. 2, September 2019, pp. 1-14

Abstract:

The present article concerns main functional features, working principles, technical device advantages of the vortex mixer named Maxwell's demon after the genial American physicist J.C. Maxwell. On the base of a multi-aspect study experimental data and results the authors state considerable technical and economic effects of the vortex furnaces every-day life and wide-scale industrial use. Numerous schemes and figures presented in the article help to get an adequate idea of the invention in question.

Keywords:

door keeper, device, vessel, process, heating energy, experiment, vortex furnace, mixer, outlet

Full Text:

References:

  1. Govorov V.I., Plotnikov V.M., Karatay E.V. –. Theoretical foundations of burning and explosion.- Temirtau: KGIU, 2007 (7.4. Burning acceleration factors).
  2. Fujita T. A detailed analysis of the Fargo tornadoes of June, 1957, Res. Pap., Nо 42 Weather Bur. Unit. Stat., 1960.
  3. Merkulov А. P. Vortex effect and its using in technics. — Samaa: Optima, 1997.
  4. Nevolin V.G. The experience of sound effect using in Perm region oil production practice.– Perm, 2008.
  5. Semenov N.N. Chain reactions. L.: ONTI, 1934; II edition. M.: Science, 1986.
  6. Schauberger V. Water energy. - Yausa: Eksmo, 2007.
  7. Styrikovitch M.A. Solid fuel combustion problems in big energetics. -M.: Science, 1989.
  8. Suslov A.D., Ivanov S.V., Murashkin А. V., Chizhikov Y.V. Vortex aggregates. — M.: Machine building, 1985.
  9. Wobus H. B. Tornado from cumulo-nimbus. Bull.Amer. Met. Soc. v.21, Nо 9, 1940, pp.367-368.
  10. Zeldovitch Y.B., Barenblatt G.I., Librovitch V. B., Mahviladze G.M. Mathematical theory of burning and explosion — M.: Science, 1980.

DOI

Paper Title

10.21058/gjecs.2019.42002

DESIGN AND IMPLEMENTATION OF LOW POWER THERMAL AWARE ATM

Author Name

Volume No., Issue No., Year, & Page No.

Kavya Dwivedi,

Vol. 4, No. 2, September 2019, pp. 1-5

Abstract:

In this Paper, we have designed a Automated Teller Machine (ATM) which is electromechanical machine works in different temperature. We analysed the Static Power at discrete temperature that is thermal scaling of ATM at XILNIX 14.1 ISE Design Suit. In this paper we have used two FGPA family one is Spartan which is Spartan 6 and another is Virtex which is Virtex 4. We have distinguished on chip power by varying the Ambient temperature from 50°C to 5°C and we observed when we lowered the temperature of both FGPA families automatically the leakage power lowered that determine our ATM are worked in any temperature without disturbing its functionality. .

Keywords:

Ambient Temperature, Thermal Scaling, Xilinx, Verilog, FGPA.

Full Text:

References:

  1. Bishwajeet Pandey, Keshav Kumar, Shabeer Ahmad, Amit K Pandit, Deepa Singh and D M Akbar Hussain “Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA” in International Journal of Innovative Technology and Exploring Engineering (IJITEE) Volume-8, Issue- 9S2, July 2019.
  2. Chmiel, J. Mocha, E. Hrynkiewicz, and A. Milik. "Central processing units for PLC implementation in Virtex-4 FPGA." IFAC Proceedings Volumes 44, no. (2011): 7860-7865.IEEE Conference on Information & Communication Technologies, pp. 128-131. IEEE, 2013.
  3. Tuan, Tim, et al. "A 90nm low-power FPGA for battery-powered applications." Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays. ACM, 2006.
  4. Pandey, B., & Kumar, R. (2013, April). Low voltage DCI based low power VLSI circuit implementation on FPGA. In 2013 IEEE Conference on Information & Communication Technologies (pp. 128-131). IEEE.
  5. Belhadj, Hichem, et al. "Power-aware FPGA design." Actel Corporation White Paper 75 (2009).
  6. E.B. Kavun, and T. Yalcin. "RAM-based ultra-lightweight FPGA implementation of PRESENT." In 2011 International Conference on Reconfigurable Computing and FPGAs, pp. 280-285. IEEE, 2011.
  7. Vereecken, Willem, Ward Van Heddeghem, Didier Colle, Mario Pickavet, and Piet Demeester. "Overall ICT footprint and green communication technologies." In 2010 4th International Symposium on Communications, Control and Signal Processing (ISCCSP), pp. 1-6. IEEE, 2010.
  8. https://www.igi-global.com/dictionary/key-issues-and-research-directions-in-green-wireless-networking/43606 (17/06/2019).
  9. Curd, Derek. "Power consumption in 65 nm FPGAs." Xilinx white paper 711 (2007).
  10. Pandey, B., Thind, V., Sandhu, S. K., Walia, T., & Sharma, S. (2015). SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA. International Journal of Security and Its Application, 9(7), 267-274.

DOI

Paper Title

10.21058/gjecs.2019.42003

HSTL and HSUL I/O Standard Based Energy-Efficient Control Unit Circuit Design on FPGA

Author Name

Volume No., Issue No., Year, & Page No.

Keshav Kumar, Pushpanjali Pandey, Rajina R. Mohamed

Vol. 4, No. 2, September 2019, pp. 1-7

Abstract:

World is facing a huge problem of power deficiency. That’s why power and energy-efficient devices are getting more attention these days. This work highlights the energy-efficient control design implementation on 28nm technology Artix-7 Field Programmable Gate Array (FPGA). The implementation is done on the Vivado 2014.2 Design Suite. In this work, the Input/Output (I/O) Standard is varied at both input and output end of control unit circuit for calculating the power utilization of the control unit circuit with 28-nm FPGA. It is observed that High-Speed Unterminated Logic (HSUL_12) I/O Standard consumes the least amount of power when the control unit circuit is implemented on 28-nm FPGA.

Keywords:

Control unit, FPGA, I/O Standard, Energy, and Power.

Full Text:

References:

  1. www.conserve-energy-future.com/causes-and-solution-to-the-global-energy-crisis.php
  2. R. Mahapatra, Y. Nijsure, G. Kaddoum, N.Ul. Hassan, and C. Yuen. Energy efficiency tradeoff mechanism towards wireless green communication: A survey. IEEE Communications Surveys & Tutorials 18, no. 1 (2015): 686-705.
  3. S. M T. Siddiquee, K. Kumar, B. Pandey, A. Kumar,” Energy Efficient Instruction Register for Green Communication”, International Journal of Engineering and Advanced Technology (IJEAT), Volume-8, Issue-2S2, January 2019.
  4. K. Kumar, S. Ahmad, B. Pandey, A. K. Pandit, D. Singh, D. M. A.Hussain "Power Efficient Frequency Scaled and Thermal-Aware Control Unit Design on FPGA”, International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 8, Issue-9S2, July 2019.
  5. P. R. Singh, B. Pandey, T. Kumar, and T. Das. "I/O standard- based-power optimized processor register design on ultra-scale FPGA." In 2014 International Conference on Computing for Sustainable Global Development (INDIACom), pp. 172-177. IEEE, 2014.
  6. K. Goswami, B. Pandey, T. Kumar, and D.M A.Hussain. "Different I/O Standard and Technology-Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green Wireless Communication on FPGA." Wireless Personal Communications 96, no. 2 (2017): 3139-3158.
  7. K. Goswami, and B. Pandey. "Reduction of I/O power using energy efficient HSTL I/O standard in vedic multiplier on FPGA." In 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 1514-1518. IEEE, 2015.
  8. https://en.wikipedia.org/wiki/High-speed_transceiver_logic
  9. https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf
  10. T. Das, B. Pandey, M. A. Rahman, and T. Kumar. "SSTL based green image ALU design on different FPGA." In 2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE), pp. 146-150. IEEE, 2013
  11. M. Bansal, N. Bansal, R. Saini, B. Pandey, L. Kalra, and D. M A. Hussain. "SSTL I/O Standard-based environment-friendly energy-efficient ROM design on FPGA." In 3rd International Symposium on Environmental Friendly Energies and Applications (EFEA), pp. 1-6. IEEE, 2014
  12. K. Kalia, K. Nanda, S. Malhotra, and B. Pandey. "HSTL based low power thermal aware adder design on 65nm FPGA." In 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 1490-1495. IEEE, 2015.
  13. K. Kumar, A. Kaur, B. Pandey, and S. N. Panda. "Low Power UART Design Using Different Nanometer Technology-Based FPGA." In 2018 8th International Conference on Communication Systems and Network Technologies (CSNT), pp. 1-3. IEEE, 2018.
  14. B. Pandey, and M. Pattanaik. "Low power VLSI circuit design with efficient HDL coding." In 2013 International Conference on Communication Systems and Network Technologies, pp. 698-700. IEEE, 2013.
  15. K. Goswami, and B. Pandey. "Voltage scaling based low power high- performance Vedic multiplier design on FPGA." In 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom), pp. 1529-1533. IEEE, 2015.
  16. B. Pandey, A. Kaur, T. Kumar, T. Das, M. A. Rahman, and D. M. A. Hussain. "LVTTL based energy efficient watermark generator design and implementation on FPGA." In 2014 International Conference on Information and Communication Technology Convergence (ICTC), pp. 642-646. IEEE, 2014.
  17. B. Pandey, K. Kumar, S. Ahmad, A. K. Pandit, D. Singh, D.M A. Hussain" Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA”, International Journal of Innovative Technology and Exploring Engineering (IJITEE) Volume-8 Issue- 9S2, July 2019
  18. K. Kumar, A. Kaur, S. N. Panda, and B. Pandey. "Effect of Different Nano Meter Technology-Based FPGA on Energy Efficient UART Design." In 2018 8th International Conference on Communication Systems and Network Technologies (CSNT), pp. 1-4. IEEE, 2018.

DOI

Paper Title

10.21058/gjecs.2019.42004

Impact of Foreign Direct Investment on Economic Growth of Pakistan

Author Name

Volume No., Issue No., Year, & Page No.

Mahreen Zain

Vol. 4, No. 2, September 2019, pp. 1-12

Abstract:

Foreign direct investment (FDI) is mostly considered as a significant constituent for the overall economic growth of a country. The current research aims to examine the impact of FDI on economic growth of Pakistan. This study uses the time series data from 2000 to 2016. Correlation and Regression analysis in SPSS software were used to analyze the data. The results obtained from the statistical analysis reveal that FDI is positively related to the economic growth of Pakistan.

Keywords:

FDI, GDP, Pakistan.

Full Text:

References:

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DOI

Paper Title

10.21058/gjecs.2019.42005

Designing of sliding mode observer for the position control for quadrotor UAV

Author Name

Volume No., Issue No., Year, & Page No.

DING LI

Vol. 4, No. 2, September 2019, pp. 1-12

Abstract:

Aiming at the model uncertainty in system and vulnerability to external environment disturbance for the quadrotor UAV in field flight, this article uses the following ideas to solve them. Firstly, use the Newton-Euler method to establish the system model. Then, according to the inner and outer loop control structure, use the attitude command of the output of outer loop position controller as the input of inner loop attitude controller. This paper concentrates to designing of sliding mode observer controller. In addition, the stability of position subsystem proved by Lyapunov theory, the resulted conclusion state that the error converges to zero in finite time. Finally, the simulation of fixed-point control shows that the controller has fast response speed, anti-interference performance, and can track quickly and accurately.

Keywords:

quadrotor, UAV controlling, SMC.

Full Text:

References:

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DOI

Paper Title

10.21058/gjecs.2019.42006

Low-cost smart-home for rural areas of Pakistan

Author Name

Volume No., Issue No., Year, & Page No.

Sajida Mirani, Abdul Karim Mirjat, Liaquat A. Thebo, Sana H. Jokhio, Imran A. Jokhio

Vol. 4, No. 2, September 2019, pp. 1-9

Abstract:

A number of issues and challenges are associated with the lives of people living in the rural areas of Pakistan due to natural disasters and other hazards. Wireless sensor networks are being used in a number of applications that can provide timely relief in hazardous or disastrous conditions. In this paper a wireless sensor network based low-cost smart-home network has been proposed to provide comfort and timely relief to the residents of rural areas under consideration. A prototype has been designed and implemented in two phases; simulation and hardware implementation. The simulation outlines the possible challenges that may be faced during the hardware implementation. The hardware implementation phase involves actual sensing and processing using hardware devices. The proposed prototype is tested and evaluated in real time.

Keywords:

WSN, Smart-home, Low-cost .

Full Text:

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